1. Field of the Disclosure
The present disclosure generally relates to synchronous circuits and, more particularly, to a single delay line based structure to provide for a seamless phase change between coarse and fine delays at high frequencies.
2. Brief Description of Related Art
Most digital logic implemented on integrated circuits is clocked synchronous sequential logic. In electronic devices such as synchronous dynamic random access memory circuits (SDRAMs), microprocessors, digital signal processors, etc., the processing, storage, and retrieval of information is coordinated or synchronized with a clock signal. The speed and stability of the clock signal determines to a large extent the data rate at which a circuit can function. Many high speed integrated circuit devices, such as SDRAMs, microprocessors, etc., rely upon clock signals to control the flow of commands, data, addresses, etc., into, through and out of the devices.
In SDRAMs or other semiconductor memory devices, it is desirable to have the data output from the memory synchronized with the system clock that also serves the microprocessor. Delay-locked loops (DLLs) are synchronous circuits used in SDRAMs to synchronize an external clock (e.g., the system clock serving a microprocessor) and an internal clock (e.g., the clock used internally within the SDRAM to perform data read/write operations on various memory cells) with each other. Typically, a DLL is a feedback circuit that operates to feed back a phase difference-related signal to control a delay line, until the timing of one clock signal (e.g., the system clock) is advanced or delayed until its rising edge is coincident (or “locked”) with the rising edge of a second clock signal (e.g., the memory internal clock).
FIG. 1 depicts a simplified block diagram of a delay-locked loop (DLL) 10. The DLL 10 receives a reference clock (RefClk) 12 as an input and generates an output clock or the ClkOut signal 14 at its output. The ClkOut signal 14 is, in turn, fed back as a feedback clock (ClkFB or FBClock) 16 as discussed later. The reference clock 12 is interchangeably referred to herein as “ClkREF”, “RefClk”, “Ref clock signal” or “Ref clock”; whereas the feedback clock 16 is interchangeably referred to herein as “ClkFB”, “ClkFB signal”, “FB clock signal” or “FBClock,” The reference clock 12 is typically the external system clock serving the microprocessor or a delayed/buffered version of it. The system clock 12 may be supplied to the DLL 10 via one or more clock buffers (not shown).
The delay line in the DLL 10 may be comprised of a coarse delay line 18 and a fine delay line 20. The RefClk 12 may be supplied first to the coarse delay line 18 whose output is then fed into the fine delay line 20 to generate the ClkOut signal 14. The coarse delay line 18 may include a number of coarse delay stages (not shown) and may be designed to produce an output signal having a phase variation from an input signal within a coarse delay stage, whereas the fine delay line 20 is typically designed to produce an output signal having a phase variation from the input signal which is substantially smaller than the deviation provided by the coarse delay line 18. In other words, the coarse delay line 18 is designed to bring its output signal to a near phase lock condition, or phase delayed condition, whereas the fine delay line 20 is designed to perform “fine tuning” to achieve the signal locking condition. Thus, a dual delay line (coarse and fine) DLL or PLL can provide a wide lock range while at the same time still providing a tight lock within reasonable time parameters.
In operation, the clock output signal 14 is used to provide the internal clock (not shown) used, for example, by a memory device (not shown) to perform data read/write operations on memory cells (not shown) and to transfer the data out of the memory device to the data requesting device (e.g., a microprocessor (not shown)). As can be seen from FIG. 1, the ClkOut signal 14 (and, hence, the FBClock 16) is generated using delay lines 18, 20, which introduce a specific delay into the input Ref clock 12 to obtain the “lock” condition.
As noted before, the purpose of the DLL 10 is to align or lock the internal clock (not shown) used by, for example, a memory device to perform data read/write operations to the system's external clock (not shown). A delay monitor 22 monitors a delay time of the output clock 14 from the coarse and fine delay lines 18, 20. A phase detector (PD) 24 compares the relative timing of the edges of the system's external clock (not shown) and the memory's internal clock (not shown) by comparing the relative timing of their respective representative signals—the Ref clock 12 which relates to the system clock, and the FBClock signal 16 which relates to the memory's internal clock—so as to establish the lock condition. The PD 24 may compare a phase difference between the RefClk 12 and the FBClock 16 (supplied via the delay monitor 22) and output appropriate shift signals SHL (Shift Left) signal 25 and SHR (Shift Right) signal 26 for adjusting the phase difference between the RefClk 12 and the ClkOut 14. The delay monitor circuit 22 may function as a buffer or dummy delay circuit for the ClkOut signal 14 before the ClkOut signal 14 is fed into the phase detector 24 as the FB clock 16. The output of the delay monitor 22 (i.e., the FB clock 16) may effectively represent the memory's internal clock, which may be provided to various circuit elements in a memory device through the clock driver and data output stages (not shown). Thus, the delay monitor 22 attempts to maintain the phase relationship between the Ref clock 12 and the FB clock 16 as close as possible to the phase relationship that exists between the external system clock (not shown) and the electronic device's (e.g., a memory's) internal clock (not shown).
The Ref clock 12 and the FB clock 16 are fed as inputs into the phase detector 24 for phase comparison. The output of the PD 24—one of the SHL 25 and SHR 26 signals—controls the amount of delay imparted to the RefClk 12 by the delay lines 18, 20. The SHL 25 and SHR 26 signals may determine whether the Ref clock 12 should be shifted left (SHL) or shifted right (SHR) through the appropriate delay units in the delay lines 18, 20 so as to match the phases of the Ref clock 12 and the FB clock 16 to establish the lock condition. The SHL 25 and SHR 26 signals may be supplied to the delay lines 18, 20 via a shift register 28, which may control the delay time of the delay lines 18, 20 according to the shift signals SHL and SHR from the phase detector 24. Based on the status of the SHL 25 and SHR 26 signals input thereto, the shift register 28 may generate one or more delay adjustment signals 30 to carry, out the left or right shift operations indicated by the phase detector 24 (via SHL 25 or SHR 26 signals). As is known in the art, a shift left operation in a delay line results in adding a delay to the clock signal input thereto, whereas a shift right operation reduces the delay. The delay adjustment signals 30 essentially serve the same purpose as the SHL 25 or the SHR 26 signals, but their application to the coarse and fine delay lines 18, 20, respectively, is controlled by the shift register 28. The cumulative delay imparted to the Ref clock 12 by the series-connected coarse and fine delay lines 18 and 20, respectively, operates to adjust the time difference between the output clock 14 (as represented by the FB clock 16) and the input RefClk 12 until they are aligned. The phase detector 24 generates the shift left (SHL) and shift right (SHR) signals depending on the detected phase difference or timing difference between the Ref clock 12 and the FB clock 16, as is known in the art.
In the DLL 10 of FIG. 1, when the RefClk 12 is output from the coarse delay line 18 and input to the fine delay line 20, the switching at the boundary of coarse and fine delays may result in creation of jitter(s) or discontinuity in the final signal output from the fine delay line 20 (i.e., the ClkOut signal 14). These clock perturbations may not be desirable, especially when an electronic device (e.g., a memory device (not shown)) is operated at significantly high clock frequencies (e.g., 800 MHz or higher). Furthermore, as reference clock frequencies increase, the DLL architecture in FIG. 1 may not be suitable to adequately control coarse shifting at, such high frequencies, which may negatively affect the signal integrity of the output clock 14 and may also delay establishment of a lock condition.
It is therefore desirable to devise a clock synchronization circuit that avoids output clock signal jitter at high clock frequencies and that also performs a smooth phase transition at the boundary of the coarse and fine delays. It is also desirable to have this synchronization circuit able to adequately control coarse shifting at higher clock frequencies without any limitations.